TECHNICAL ARTICLES

hardware interference

Who Needs a Hypervisor?

Picture of Tim Loveless | Principal Solutions Architect

Tim Loveless | Principal Solutions Architect: Feb 25, 2021 12:59:58 PM

_______________ The standard benefits of a hypervisor are well known and often touted. Every RTOS has its hypervisor and they do genuinely help embedded designers to: Partition multicore processors into virtual machines; an elegant way to... Read More

What is Cache Coloring and How Does it Work?

Tim Loveless | Principal Solutions Architect: Feb 5, 2021 11:52:40 AM

_______________ There are substantial challenges in building secure and safe systems on multicore processors (MCPs). Last level cache contention is undoubtedly the largest source of multicore interference, and a significant challenge for real-time... Read More

Challenges Building Safe Multicore Systems

Tim Loveless | Principal Solutions Architect: Jun 15, 2020 8:12:09 AM

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