--- title: Lynx Software Technologies | Learning Center | hardware description: hardware | --- # TECHNICAL ARTICLES Filter by Tag Show All 10G Arm Tech Con Automotive Avionics BSPs Benchmark CAST-32A CVEs Cache Allocation Technology Cache-partitioning Certification DO-178 Demo Events FAA FACE TIM Future Airborne Capabilities Environment (FACE™) Least Privilege Lynx MOSA.ic™ LynxElement LynxOS-178 LynxSecure MCP Multi-core Multicore Open Group Open Standards Open Systems PCI-E POSIX® Press Release RAM Ram Disk Reference Architecture SR-IOV Safety Security Single-root IO Virtualization Standards Subjects Systems Architecture TC-16/51 TCO TTM Technical Blog Trusted Codebase Virtual Machines architecture board support certifications costs development embedded linux embedded systems hardware hardware interference hypervisors linux meltdown partitioning privilege escalation real-time reusable software rsc rtos separation kernel side channels software spectre virtualization vulnerabilities ### hardware [![](https://www.lynx.com/hubfs/SR-IOV%20diagram%20002b.png) ](https://www.lynx.com/embedded-systems-learning-center/what-is-single-root-io-virtualization-part-2) #### [Single Root I/O Virtualization (SR-IOV) -Pt 2- LynxOS-178 10G network benchmarkS](https://www.lynx.com/embedded-systems-learning-center/what-is-single-root-io-virtualization-part-2) ![Picture of Tim Loveless | Principal Solutions Architect](https://www.lynx.com/hs-fs/hubfs/Tim_Loveless-Photo.jpg?width=30&name=Tim_Loveless-Photo.jpg) [Tim Loveless | Principal Solutions Architect: ](https://www.lynx.com/embedded-systems-learning-center/author/tim-loveless-principal-solutions-architect) Mar 16, 2021 12:33:11 PM _______________ Single Root I/O Virtualization (SR-IOV) virtualizes network interface cards (NICs) to allow a single NIC to present itself as dozens of virtual NICs to a hypervisor. It is a hardware standard, part of the PCI-SIG (Peripheral... [Read More](https://www.lynx.com/embedded-systems-learning-center/what-is-single-root-io-virtualization-part-2) [![](https://www.lynx.com/hubfs/Diagram%20for%20Tim%20007%20final.png) ](https://www.lynx.com/embedded-systems-learning-center/do-you-need-a-hypervisor) #### [Who Needs a Hypervisor?](https://www.lynx.com/embedded-systems-learning-center/do-you-need-a-hypervisor) ![Picture of Tim Loveless | Principal Solutions Architect](https://www.lynx.com/hs-fs/hubfs/Tim_Loveless-Photo.jpg?width=30&name=Tim_Loveless-Photo.jpg) [Tim Loveless | Principal Solutions Architect: ](https://www.lynx.com/embedded-systems-learning-center/author/tim-loveless-principal-solutions-architect) Feb 25, 2021 12:59:58 PM _______________ The standard benefits of a hypervisor are well known and often touted. Every RTOS has its hypervisor and they do genuinely help embedded designers to: Partition multicore processors into virtual machines; an elegant way to... [Read More](https://www.lynx.com/embedded-systems-learning-center/do-you-need-a-hypervisor) [![](https://www.lynx.com/hubfs/cache%20coloring%20thumbnail-1.png) ](https://www.lynx.com/embedded-systems-learning-center/what-is-cache-coloring) #### [What is Cache Coloring and How Does it Work?](https://www.lynx.com/embedded-systems-learning-center/what-is-cache-coloring) ![Picture of Tim Loveless | Principal Solutions Architect](https://www.lynx.com/hs-fs/hubfs/Tim_Loveless-Photo.jpg?width=30&name=Tim_Loveless-Photo.jpg) [Tim Loveless | Principal Solutions Architect: ](https://www.lynx.com/embedded-systems-learning-center/author/tim-loveless-principal-solutions-architect) Feb 5, 2021 11:52:40 AM _______________ There are substantial challenges in building secure and safe systems on multicore processors (MCPs). Last level cache contention is undoubtedly the largest source of multicore interference, and a significant challenge for real-time... [Read More](https://www.lynx.com/embedded-systems-learning-center/what-is-cache-coloring) [![](https://www.lynx.com/hubfs/multicore%20sys%20architecture%2001%20spacing.png) ](https://www.lynx.com/embedded-systems-learning-center/challenges-building-safe-multicore-mcp-software-systems) #### [Challenges Building Safe Multicore Systems](https://www.lynx.com/embedded-systems-learning-center/challenges-building-safe-multicore-mcp-software-systems) ![Picture of Tim Loveless | Principal Solutions Architect](https://www.lynx.com/hs-fs/hubfs/Tim_Loveless-Photo.jpg?width=30&name=Tim_Loveless-Photo.jpg) [Tim Loveless | Principal Solutions Architect: ](https://www.lynx.com/embedded-systems-learning-center/author/tim-loveless-principal-solutions-architect) Jun 15, 2020 8:12:09 AM _______________ [Read More](https://www.lynx.com/embedded-systems-learning-center/challenges-building-safe-multicore-mcp-software-systems) [![](https://www.lynx.com/hubfs/Commercial%20kernels%2002.png) ](https://www.lynx.com/embedded-systems-learning-center/what-is-a-separation-kernel) #### [What Is A Separation Kernel?](https://www.lynx.com/embedded-systems-learning-center/what-is-a-separation-kernel) ![Picture of Tim Loveless | Principal Solutions Architect](https://www.lynx.com/hs-fs/hubfs/Tim_Loveless-Photo.jpg?width=30&name=Tim_Loveless-Photo.jpg) [Tim Loveless | Principal Solutions Architect: ](https://www.lynx.com/embedded-systems-learning-center/author/tim-loveless-principal-solutions-architect) Mar 22, 2020 12:02:33 PM _______________ Having built both separation kernels and real-time operating systems—and supported customers using both across a wide range of industries—we are familiar with the pros and cons of each software technology, as well as their security,... [Read More](https://www.lynx.com/embedded-systems-learning-center/what-is-a-separation-kernel) [![](https://www.lynx.com/hubfs/SCSC%20png.png) ](https://www.lynx.com/embedded-systems-learning-center/safety-critical-systems-symposium-2020) #### [Field Notes: Safety-Critical Systems Symposium 2020](https://www.lynx.com/embedded-systems-learning-center/safety-critical-systems-symposium-2020) ![Picture of Tim Loveless | Principal Solutions Architect](https://www.lynx.com/hs-fs/hubfs/Tim_Loveless-Photo.jpg?width=30&name=Tim_Loveless-Photo.jpg) [Tim Loveless | Principal Solutions Architect: ](https://www.lynx.com/embedded-systems-learning-center/author/tim-loveless-principal-solutions-architect) Feb 24, 2020 12:34:50 PM _______________ [Read More](https://www.lynx.com/embedded-systems-learning-center/safety-critical-systems-symposium-2020) [![](https://www.lynx.com/hubfs/TC-16-51%20BG%2005.png) ](https://www.lynx.com/embedded-systems-learning-center/tc-16-51-adding-bottom-up-interference-analysis-for-mcps) #### [TC-16/51: Adding Bottom Up Interference Analysis for MCPs](https://www.lynx.com/embedded-systems-learning-center/tc-16-51-adding-bottom-up-interference-analysis-for-mcps) ![Picture of Mark Brown | Systems Architect](https://www.lynx.com/hs-fs/hubfs/20190910b_MarkBrown.jpg?width=30&name=20190910b_MarkBrown.jpg) [Mark Brown | Systems Architect: ](https://www.lynx.com/embedded-systems-learning-center/author/mark-brown-systems-architect) Jan 28, 2020 2:20:00 PM _______________ I hadn't heard of "bottom up" avionics certification before I read FAA's TC-16/51. But now, looking back at it, I think the authors from Thales Avionics, including Xavier Jean, PhD, proposed a big change in perspective. In their own... [Read More](https://www.lynx.com/embedded-systems-learning-center/tc-16-51-adding-bottom-up-interference-analysis-for-mcps) [![](https://www.lynx.com/hubfs/Intel%C2%AE%20SR-IOV%20NICs%20+%20Lynx%20MOSA.ic%E2%84%A2%20jpg2.jpg) ](https://www.lynx.com/embedded-systems-learning-center/what-is-sr-iov-and-why-is-it-important-for-embedded-devices) #### [What is SR-IOV and Why is It Important for embedded devices?](https://www.lynx.com/embedded-systems-learning-center/what-is-sr-iov-and-why-is-it-important-for-embedded-devices) ![Picture of Tim Loveless | Principal Solutions Architect](https://www.lynx.com/hs-fs/hubfs/Tim_Loveless-Photo.jpg?width=30&name=Tim_Loveless-Photo.jpg) [Tim Loveless | Principal Solutions Architect: ](https://www.lynx.com/embedded-systems-learning-center/author/tim-loveless-principal-solutions-architect) Oct 7, 2019 2:09:00 PM Single Root I/O Virtualization (SR-IOV) is the complex name for a technology beginning to find its way into embedded devices. SR-IOV is a hardware standard that allows a PCI Express device – typically a network interface card (NIC) – to present... [Read More](https://www.lynx.com/embedded-systems-learning-center/what-is-sr-iov-and-why-is-it-important-for-embedded-devices) [![](https://www.lynx.com/hubfs/Lynx%20Software%20Technologies%20-%20BSP.jpg) ](https://www.lynx.com/embedded-systems-learning-center/cost-of-board-support-packages-bsps) #### [What is the Cost of a Board Support Package?](https://www.lynx.com/embedded-systems-learning-center/cost-of-board-support-packages-bsps) ![Picture of Tim Loveless | Principal Solutions Architect](https://www.lynx.com/hs-fs/hubfs/Tim_Loveless-Photo.jpg?width=30&name=Tim_Loveless-Photo.jpg) [Tim Loveless | Principal Solutions Architect: ](https://www.lynx.com/embedded-systems-learning-center/author/tim-loveless-principal-solutions-architect) Oct 1, 2019 10:35:00 AM _______________ [Read More](https://www.lynx.com/embedded-systems-learning-center/cost-of-board-support-packages-bsps) [![](https://www.lynx.com/hubfs/Design%20prevails%2002.png) ](https://www.lynx.com/embedded-systems-learning-center/design-prevails-protecting-systems-from-meltdown-and-spectre) #### [Design Prevails: Protecting Systems from Meltdown and Spectre](https://www.lynx.com/embedded-systems-learning-center/design-prevails-protecting-systems-from-meltdown-and-spectre) ![Picture of Will Keegan | CTO](https://www.lynx.com/hs-fs/hubfs/Exec-thumbs-Will-1.jpg?width=30&name=Exec-thumbs-Will-1.jpg) [Will Keegan | CTO: ](https://www.lynx.com/embedded-systems-learning-center/author/will-keegan-cto) Feb 19, 2018 10:21:00 AM _______________ [Read More](https://www.lynx.com/embedded-systems-learning-center/design-prevails-protecting-systems-from-meltdown-and-spectre)