TECHNICAL ARTICLES

CAST-32A

Who Needs a Hypervisor?

Picture of Tim Loveless | Principal Solutions Architect

Tim Loveless | Principal Solutions Architect: Feb 25, 2021 12:59:58 PM

_______________ The standard benefits of a hypervisor are well known and often touted. Every RTOS has its hypervisor and they do genuinely help embedded designers to: Partition multicore processors into virtual machines; an elegant way to... Read More

What is Cache Coloring and How Does it Work?

Tim Loveless | Principal Solutions Architect: Feb 5, 2021 11:52:40 AM

_______________ There are substantial challenges in building secure and safe systems on multicore processors (MCPs). Last level cache contention is undoubtedly the largest source of multicore interference, and a significant challenge for real-time... Read More

Challenges Building Safe Multicore Systems

Tim Loveless | Principal Solutions Architect: Jun 15, 2020 8:12:09 AM

_______________ Read More

Field Notes: Safety-Critical Systems Symposium 2020

Tim Loveless | Principal Solutions Architect: Feb 24, 2020 12:34:50 PM

_______________ Read More

TC-16/51: Adding Bottom Up Interference Analysis for MCPs

Picture of Mark Brown | Systems Architect

Mark Brown | Systems Architect: Jan 28, 2020 2:20:00 PM

_______________ I hadn't heard of "bottom up" avionics certification before I read FAA's TC-16/51. But now, looking back at it, I think the authors from Thales Avionics, including Xavier Jean, PhD, proposed a big change in perspective. In their own... Read More

CAST-32A: Significance and Implications

Mark Brown | Systems Architect: Nov 15, 2018 10:36:00 AM

_______________ CAST-32A presents the coordinated position of avionics certification authorities regarding Multi-Core Processors (MCPs). While today’s aerospace ecosystem could benefit from the use of MCPs, before CAST-32A was published, FAA/EASA... Read More